Workshop Program

Workshop Agenda*

20 March 2016
7:30 - 8:15 Registration and Breakfast
8:15 - 8:30 Welcome Remarks
8:30 - 10:00 Session 1: Overview of Integrated Photonics
10:00 - 10:20 Coffee Break
10:20 - 11:45 Session 2: Integrated Photonic Roadmaps
11:45 - 13:30 Lunch Break and Poster Session
13:30 - 15:30 Session 3: Trends in the Advanced Packaging Supply Chain
15:30 - 16:00 Coffee Break
16:00 - 17:30 Session 4: Challenges and Requirements
17:30 - 18:00 Session 5: Discussion Group Readouts
18:00 - 19:00 Networking Reception
*times are subject to change
 

Workshop Sessions

Session 1: Overview of Integrated Photonics
Moderator: Madeleine Glick, Senior Research Scientist, University of Arizona
Speakers will provide a big picture perspective of the customer demands and technical requirements, including details about unit volumes, costs, etc.  Where is the state of the art for integrated photonics with respect to key applications?  Particular focus will be on the challenges of reducing cost and realizing high volume manufacturable platforms, and market trends and opportunities.

Photonic Integrated Circuits for Access and Transport Networks
Y.K. Chen, Director, Bell Laboratories, Nokia
In this talk, we will review recent advances in the semiconductor photonic components, photonic integrated circuits and the integration methodologies implemented on the traditional compound semiconductor as well as the emerging CMOS-compatible silicon platform.

Thomas Koch, Dean, College of Optical Sciences, University of Arizona
Abstract available soon.

Optical Interfaces as Key Enablers for Data Centers - a Life Cycle View of Drivers & Challenges
Katharine Schmidtke, Optical Technology Strategy, Facebook
The migration to 100G-based datacenters is underway and requires new approaches for optical interfaces. The classical challenges of driving reductions in cost, footprint and power are accompanied by the need to ramp up very quickly for high volume deployments. Data center requirements differ from those of the traditional Telecommunication equipment central offices in many ways—making it possible to optimize for shorter life-times, relaxed environmental conditions (e.g. temperature, humidity, and mechanics), and also reduced link budgets. These less stringent requirements mean that innovations can shift away from performance to focus on mass manufacturing, simplified packaging, and reduced power. This dynamic is accelerating the upgrades from 100G-based fiber infrastructure to 200G and 400G as the network, storage and compute requirements change.        


Session 2: Integrated Photonic Roadmaps
Moderator: Dan Kilper, Administrative Director CIAN, University of Arizona
A review of the efforts to address volume manufacturing of integrated photonics, including co-packaging of photonics and electronics.  There are several initiatives worldwide aimed at addressing the ecosystem of manufacturing integrated photonics, each with its own emphasis.  Speakers will give short presentations on the vision of these initiatives, and then there will be an open discussion of the overlap and the gaps.

Integrated Photonics Packaging in Japan
Takahiro Nakamura, Photonics Electronics Technology Research Association (PETRA)
PETRA is working in research and development for new generation device and networking technology by utilizing photonics electronics convergence technology,under Photonics Electronics Convergence Technology for Power-Reducing Jisso System project supported by the Minister of Economy, Trade and Industry (METI) for FY2012 and The New Energy and Industrial Technology Development Organization (NEDO) from FY2013. Jisso is concept of overall packaging technology from devices to systems in Japanese. The key word of this project is significantly reduction, size, power consumption and cost, through implementation and integration of key technologies which utilize electronics and photonics circuits. Jisso (Packaging) technology plays an important part to connect between photonics electronics integrated circuit and systems.
PETRA's Roadmap, development framework and current activity will be addressed in this presentation.

AIM Photonics Introduction
Michael Liehr, SUNY Polytechnic Institute, College of Nanoscale Science and Engineering, State University of New York, USA
The recently established American Institute for Manufacturing Photonics (AIM Photonics) is a manufacturing consortium headquartered in NY, with funding from the US Department of Defense (DoD), New York State, and industrial partners to advance the state of the art in the design, manufacture, testing, assembly, and packaging of integrated photonic devices. Dr. Michael Liehr, CEO of AIM Photonics, will describe the technical goals, operational framework, near-term milestones, and opportunities for the broader photonics community.

Integrated Photonics Packaging in Europe
Peter O'Brien, Head of the Photonics Packaging Group at the Tyndall National Institute
Europe has a number of flagship integrated photonics initiatives. These have focused primarily on device foundry services including Si and InP Multi Project Wafer (MPW) foundries, such as Europractice (Si-PICs) and JEPPIX(InP-PICs). As these device foundries have become well established and user numbers have grown significantly, it has become apparent that a coherent packaging strategy is required to enable these users develop the complete PIC solution. This presentation will review the integrated photonics landscape in Europe, the diversity of individual research and commercial activities, from design through to sub-system packaging, and the current strategy to develop a coherent programme for integrated photonic packaging. This includes development of a European PIC Packaging Pilot Line.

Perspective on Photonic Volume Manufacturing Gained from Participation in the iNemi, ITRS 2.0, MIT CTR and PSMC Roadmap Efforts
Richard Otte, President & CEO, PROMEX Industries, Inc.
The talk focuses on the issues that drive the cost of optoelectronic products gained from contributing to, and participating in developing, Roadmaps.  Topics addressed include the impact of the limited volume of optoelectronic products, the adoption of electronics assembly technology, the unique needs of optical devices, potential gaps and show stoppers, potential solutions and lastly “Black Swans”.


Session 3: Trends in the Advanced Packaging Supply Chain
Moderator: Peter O'Brien, Head of the Photonics Packaging Group at the Tyndall National Institute
These talks will examine advanced packaging and testing solutions and related supply chain innovations. Where is the supply chain today and where will it be in 5-10 years?  The emphasis will be on packaging and testing equipment, with a focus on automation and volume packaging, packaging foundry services, and related design rules.  This includes wafer-scale packaging and TSVs (through silicon vias).  Which areas present obstacles for lower cost manufacturing?  What is already being addressed?  

Photonic Integrated Circuits Test and Measurement
Doug Baney, Department Manager, Keysight Laboratories
Photonic Integrated circuits, PICs, are changing the technology solutions landscape with their ability to economically integrate optical functionality once the realm of stabilized optical tables. They are being applied to communications, military, and environmental sensing needs. For the foreseeable future, PICs will remain inherently analog in nature. So there are parallels, as well as significant differences, between PICs and their old uncle, microwave ASICs. Dr. Douglas Baney will discuss various test techniques employed in photonic IC characterization and likely trends this space will experience as it matures and drives to higher volumes.

Photonic Packaging in Automated, High-Throughput Microelectronic Packaging Facilities for Cost-Efficiency and Scalability
Tymon Barwicz, Research Scientist, IBM, T.J. Watson Research Center
Leveraging microelectronics wafer infrastructure for photonic wafer fabrication is enabling large scale photonic integration at a new level of yield and cost-efficiency. However, most photonic packaging approaches are still based on the telecom packaging legacy of either manual assembly or active alignment. These approaches are challenged in cost and scalability. To enable a new era of complex, low-cost photonic devices, we argue that novel packaging approaches are desired.

We have recently proposed to leverage microelectronics packaging facilities to dramatically improve assembly cost and scalability in both optical port count and manufacturing volume. This approach does not come without challenges. Above all, the placement accuracy of typical high-throughput manufacturing tools is highly inadequate for single-mode photonics. We rely on self-alignment schemes and optical mode engineering to demonstrate photonic packaging approaches that are compatible with standard, automated, high-throughput microelectronic packaging tools.   

Passive Fiber Optic Interconnect Considerations for Silicon Photonics
Mike Hughes, Director of Product Management, US Conec
A review of various proposed concepts for passive, separable fiber coupling directly to Silicon Photonic devices.  The high precision coupling requirements of these devices dictate the need for multiple developments in the manufacture of low cost components as well as the subsequent placement of the components.   Analysis of these requirements and challenges will be presented as well as a review of recent progress in the manufacture and testing of prototype silicon photonics fiber optic connectors.

Design for Packaging: Software tools to support the transition from R&D to volume manufacturing of Photonic ICs
Twan Korthorst, CEO, PhoeniX Software
This presentation will discuss today's software tools supporting design for packaging and what design challenges will be need to addressed in addition to support the industry in moving towards complete design flows allowing true design for packaging for volume applications.

How Do We Get There From Here?
Robert Patti, Founder and CTO, Tezzaron Semiconductor Corporation
Integrated photonics may someday change the world of interconnect all the way down to the device level – but how do we get there? Today’s photonic devices use unique product and assembly flows; a standard flow like that for CMOS ICs is nearly impossible to imagine. Standards have emerged for photonic cables, connectors, and protocols, but not for the devices themselves. To unleash the power of integrated photonics, we need a fully accessible ecosystem of manufacturing and flows and building blocks that echoes the CMOS ecosystem. In this talk, we will explore the missing links and discuss how we, as a manufacturer, can enable users and work to complete the supply chain.

Advanced Automated Packaging and Testing Equipment to Allow Economically-viable High Volume Manufacturing
Torsten Vahrenkamp, CEO, ficonTEC Service Gmbh
There is little doubt that the cost of packaging and testing of PIC devices will need to come down in order to foster market expansion and thus high volume manufacturing. To achieve this advanced automation is required. ficonTEC has been consistently focusing on automated photonics assembly machines since the early days of photonics. The talk will use the complex assembly of hybrid photonics transceivers to illustrates topics like flexibility vs speed, machine capital costs, cost of ownership and cost per assembled part and how this scenario will change with the increase of production volumes, and hopefully with the introduction of ‘design for manufacturing rules’.
ficonTEC is a company entirely devoted to the manufacturing of automated PIC assembly equipment, with some 350 machines installed worldwide.



Session 4: Challenges and Requirements
Moderators: Peter O'Brien, Head of the Photonics Packaging Group at the Tyndall National Institute and Tom Hausken, Senior Industry Advisor, OSA
The main obstacles to low cost, high volume integrated photonic structures and packages will be reviewed. A framework will be presented in order to identify the key challenges and quantify metrics. Participants will breakout into groups to discuss and refine this framework.


Session 5: Discussion Group Readouts

 
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